module RegisterFile (
	input [4:0] reg_source_1,
	input [4:0] reg_source_2,
	input [4:0] reg_destinate,
	input [31:0] reg_destinate_data,
	input write_enable,

	output [31:0] reg_source_1_data,
	output [31:0] reg_source_2_data
);

	// reg [31:0] registers[31:0];
	reg [31:0] registers[31:0];
	integer i;

	initial begin
		registers[0] <= 0;
		for (i = 1; i <= 32; i = i + 1)
		    begin
		        registers[i] <= 0;
		    end
	end

	assign reg_source_1_data = registers[reg_source_1];
	assign reg_source_2_data = registers[reg_source_2];

	always @ (*) begin
		if (write_enable == 1 && reg_destinate != 0) begin
			registers[reg_destinate] = reg_destinate_data;
		end
	end
	

endmodule